WRITE A VHDL PROGRAM FOR 2 TO 4 DECODER

A decoder is a multiple input, multiple output logic circuit that converts coded inputs into coded outputs where the input and output codes are different. The enable inputs must be ON for the decoder to function, otherwise its outputs assumes a ‘disabled’ output code word. Decoding is necessary in applications such as data multiplexing, seven segment display and memory address decoding.

 

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_arith.all;

use ieee.std_logic_unsigned.all;

 

entity Decoder2_4 is

port ( Enable: in STD_LOGIC;

D_IN: in STD_LOGIC_VECTOR (1 downto 0);

D_OUT: out STD_LOGIC_VECTOR (3 downto 0));

end Decoder2_4;

architecture Decoder_arc of Decoder2_4 is

begin

process (Enable,D_IN)

begin

if (Enable = '1') then

D_OUT <= "0000";

else

case D_IN is

when "00" => D_OUT <= "0001";

when "01" => D_OUT <= "0010";

when "10" => D_OUT <= "0100";

when "11" => D_OUT <= "1000";

when others => NULL;

end case;

end if;

end process;

end decoder_arc;